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| IR3502B page 1 of 38 v3.2 data sheet xphase3 tm control ic description the IR3502B control ic combined with an xphase3 tm phase ic provides a full featured and flexible way to implement a complete vr11.0 and vr11.1 power solu tion. the IR3502B provides overall system control and interfaces with any number of phase ics, each driving and monitoring a single phase. the x phase3 tm architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. features ? 1 to x phase operation with matching phase ic ? 0.5% overall system set point accuracy ? daisy-chain digital phase timing provides accura te phase interleaving without external components ? programmable 250khz to 9mhz clock oscillator freq uency provides per phase switching frequency of 250khz to 1.5mhz ? programmable dynamic vid slew rate ? programmable vid offset or no offset ? programmable load line output impedance ? high speed error amplifier with wide bandwid th of 30mhz and fast slew rate of 10v/us ? programmable constant converter output current limit during soft start ? hiccup over current protection with delay during normal operation ? central over voltage detection and latch with programmable threshold and communication to phase ics ? over voltage signal output to system with over voltage detection during powerup and normal operation ? load current reporting ? single ntc thermistor compensation for correct current reporting, oc threshold, and droop ? detection and protection of open remote sense line ? open control loop protection ? ic bias linear regulator controller ? programmable vrhot function monitors temperature of power stage through a ntc thermistor ? remote sense amplifier with true converter voltage sensing ? small thermally enhanced 32l 5mm x 5mm mlpq package ? rohs compliant ordering information device package order quantity IR3502Bmtrpbf 32 lead mlpq (5 x 5 mm body) 3000 per reel * IR3502Bmpbf 32 lead mlpq (5 x 5 mm body) 100 piece strips ? samples only
IR3502B page 2 of 38 v3.2 application circuit pgood iin vid6 vid7 eaout cv ccl cea 1 cv da c rv ccldrv rv da c rtcmp1 cfb1 rfb vid7 1 vid6 2 vid5 3 vid4 4 vid3 5 vid2 6 vccldrv 30 vid1 7 vid0 8 enable 9 hotset 11 vdac 21 vdac_buff 19 pgood 31 vsetpt 20 phsin 27 phsout 26 eaout 16 fb 15 vdrp 17 imon 32 iin 29 ss/del 22 rosc 23 vccl 28 vn 18 vrhot 10 vosen- 12 clkout 25 gnd 24 vosen+ 13 vo 14 IR3502B rdrp rfb1 cea q2 rtcmp3 rv setpt rea vccl 12v css/del phsout clkout phsin rtcmp2 +12v rtherm vid1 vid2 vid3 vid5 vid0 vosen- vosen+ vid4 vrhot rhotset1 rhotset3 vdac rosc rmon1 cmon rmon enable iout vosen- rhotset2 chotset figure 1: IR3502B application circuit figure 2 ?system-set point measurements. vdac ocset vsetpt fb eaout + - + - rosc i vsetpt isource vdac buffer amplifier isink ivdac rocset 1k fast vdac cvdac + - rosc lgnd remote sense a mplifier vo rvdac system set point voltage vosns- rosc buffer a mplifier 0.6v eaout IR3502B irosc current source generator + - vosen+ vosen- i rosc i rosc e rror a mplifier iocset IR3502B page 3 of 38 v3.2 absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these ar e stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. operating junction temperature?????..0 to 150 o c storage temperature range???????.-65 o c to 150 o c esd rating???????????????hbm class 1c jedec standard msl rating???????????????2 reflow temperature???????????.260 o c pin # pin name v max v min i source i sink 1-8 vid7-0 7.5v -0.3v 1ma 1ma 9 enable 3.5v -0.3v 1ma 1ma 10 vrhot 7.5v -0.3v 1ma 50ma 11 hotset 7.5v -0.3v 1ma 1ma 12 vosen- 1.0v -0.5v 5ma 1ma 13 vosen+ 7.5v -0.5v 5ma 1ma 14 vo 7.5v -0.5v 35ma 5ma 15 fb 7.5v -0.3v 1ma 1ma 16 eaout 7.5v -0.3v 35ma 5ma 17 vdrp 7.5v -0.3v 35ma 1ma 18 vn 7.5v -0.3v 1ma 1ma 19 vdac_buff 3.5v -0.3v 1ma 35ma 20 vsetpt 3.5v -0.3v 1ma 1ma 21 vdac 3.5v -0.3v 1ma 1ma 22 ss/del 7.5v -0.3v 1ma 1ma 23 rosc/ovp 7.5v -0.5v 1ma 1ma 24 lgnd n/a n/a 20ma 1ma 25 clkout 7.5v -0.3v 100ma 100ma 26 phsout 7.5v -0.3v 10ma 10ma 27 phsin 7.5v -0.3v 1ma 1ma 28 vccl 7.5v -0.3v 1ma 20ma 29 iin 7.5v -0.3v 1ma 1ma 30 vccldrv 10v -0.3v 1ma 50ma 31 pgood vccl + 0.3v -0.3v 1ma 20ma 32 imon 3.5v -0.3v 25ma 1ma IR3502B page 4 of 38 v3.2 electrical specifications unless otherwise specified, thes e specifications apply over: 8v vin 16v, vccl = 6.8v3.4%, -0.3v vosen- 0.3v, 0 o c t j 100 o c, 7.75k ? r osc 50.0 k ? , c ss/del = 0.1 ? f +/-10%. parameter test condition min typ max unit vdac reference vid 1v -0.5 0.5 % 0.8v vid < 1v -5 +5 mv system set-point accuracy 0.5v vid < 0.8v -8 +8 mv source & sink currents includ e ocset and vsetpt currents 30 44 58 ? a vidx input threshold 500 600 700 mv vidx input bias current 0v v(vidx) 2.5v. -1 0 1 ? a vidx off state blanking delay measure ti me till pgood drives low 0.5 1.3 2.1 ? s oscillator rosc voltage 0.570 0.595 0.620 v clkout high voltage i(clkout)= -10 ma, measure v(vccl) ? v(clkout). 1 v clkout low voltage i(clkout)= 10 ma 1 v phsout frequency r osc = 50.0 k ? 225 250 275 khz phsout frequency r osc = 24.5 k ? 450 500 550 khz phsout frequency r osc = 7.75 k ? 1.35 1.50 1.65 mhz phsout high voltage i(phsout )= -1 ma, measure v(vccl) ? v(phsout) 1 v phsout low voltage i(phsout)= 1 ma 1 v phsin threshold voltage compare to v(vccl) 30 50 70 % vdac buffer amplifier input offset voltage v(vdac_b uff) ? v(vdac), 0.5v v(vdac) 1.6v, < 1ma load -5 0 9 mv source current 0.5v v(vdac) 1.6v 0.3 0.44 0.6 ma sink current 0.5v v(vdac) 1.6v 3.5 13 20 ma unity gain bandwidth note 1 3.5 mhz slew rate note 1 1.5 v/ ? s thermal compensation amplifier output offset voltage 0v v(iin) ? v(vdac) 1.6v, 0.5v v(vdac) 1.6v, req/r2 = 2 -10 0 10 mv source current 0.5v v(vdac) 1.6v 3 8 15 ma sink current 0.5v v(vdac) 1.6v 0.3 0.4 0.5 ma unity gain bandwidth note 1, req/r2 = 2 2 4.5 7 mhz slew rate note 1 5.5 v/ ? s current report amplifier output offset voltage v(vdrp )?v(vdac) = 0,225,450,900mv -15 0 15 mv IR3502B page 5 of 38 v3.2 parameter test condition min typ max unit source current 0.5v v(imon) 0.9v 5 9 15 ma sink resistance 0.5v v(imon) 0.9v 5 10 17 k ? unity gain bandwidth note 1 1 mhz input filter time constant 1 ? s max output voltage 1.04 1.09 1.145 v soft start and delay start delay (td1) 1.0 2.9 3.5 ms soft start time (td2) 0.8 2.2 3.25 ms vid sample delay (td3) 0.3 1.2 3.0 ms pgood delay (td4 + td5) 0.5 1.2 2.3 ms oc delay time v(vdrp) ? v(dacbuff) = 1.67 mv 75 125 300 us ss/del to fb input offset voltage with fb = 0v, adjust v(ss/del) until eaout drives high 0.7 1.4 1.9 v charge current 35.0 52.5 70.0 ? a discharge current 2.5 4.5 6.5 ? a charge/discharge current ratio 10 12 16 ? a/ ? a charge voltage 3.6 4.0 4.2 v delay comparator threshold relative to charge voltage, ss/del rising 50 80 125 mv delay comparator threshold relative to charge voltage, ss/del falling 85 120 160 mv delay comparator input filter 5 ? s delay comparator hysteresis 10 30 60 mv vid sample delay comparator threshold 2.8 3.0 3.2 v discharge comp. threshold 150 200 275 mv remote sense differential amplifier unity gain bandwidth note 1 3.0 6.4 9.0 mhz input offset voltage 0.5v v(vosen+) - v(vosen-) 1.6v -3 0 3 mv sink current 0.5v v(vosen+) - v(vosen-) 1.6v 0.4 1 2 ma source current 0.5v v(vosen+) - v(vosen-) 1.6v 3 9 20 ma slew rate 0.5v v(vosen+) - v(vosen-) 1.6v 2 4 8 v/us vosen+ bias current 0.5 v < v(vosen+) < 1.6v 100 ua vosen- bias current -0.3v vosen- 0.3v, all vid codes 160 275 ua high voltage v(vccl) ? v(vo) 1.5 2 2.5 v low voltage v(vccl)=7v 50 mv error amplifier input offset voltage measure v(fb) ? v(vsetpt). note 2 -1 0 1 mv fb bias current -1 0 1 ? a vsetpt bias current r osc = 24.5 k ? 23.00 24.25 25.50 ? a dc gain note 1 100 110 120 db bandwidth note 1 20 30 40 mhz slew rate note 1 7 12 20 v/ ? s sink current 0.40 0.85 1.00 ma source current 5 8 12 ma maximum voltage measure v(vccl) ? v(eaout) 500 780 950 mv IR3502B page 6 of 38 v3.2 parameter test condition min typ max unit minimum voltage 120 250 mv open voltage loop detection threshold measure v(vccl) - v(eaout), relative to error amplifier maximum voltage. 125 300 600 mv open voltage loop detection delay measure phsout pulse numbers from v(eaout) = v(vccl) to pgood = low. 8 pulses enable input vr 11 threshold voltage enable rising 825 850 875 mv vr 11 threshold voltage enable falling 775 800 825 mv vr 11 hysteresis 25 50 75 mv bias current 0v v(enable) 3.3v -5 0 5 ? a blanking time noise pulse < 100ns will not register an enable state change. note 1 75 250 400 ns over-current comparator input offset voltage 1v v(iin) 3.3v -40 -25 -10 mv input filter time constant 2 ? s over-current threshold v drp-vdac_buff 1.07 1.17 1.27 v over-current delay counter rosc = 7.75 k ? (phsout=1.5mhz) 4096 cycle over-current delay counter rosc = 15.0 k ? (phsout=800khz) 2048 cycle over-current delay counter rosc = 50.0 k ? (phsout=250khz) 1024 cycle over-current limit amplifier input offset voltage -10 0 10 mv transconductance note 1 0.50 1.00 1.75 ma/v sink current 35 55 75 ua unity gain bandwidth note 1 0.75 2.00 3.00 khz over voltage protection (ovp) comparators threshold at power-up measure at 1.5v vccldrv 1.1 1.21 1.30 v threshold during normal operation compare to v(vdac) 105 125 145 mv ovp release voltage during normal operation compare to v(vdac) -13 3 20 mv threshold during dynamic vid down 1.70 1.73 1.75 v dynamic vid detect comparator threshold 25 50 75 mv propagation delay to iin measure time from v(vo) > v(vdac) (250mv overdrive) to v(iin) transition to > 0.9 * v(vccl). 90 180 ns iin pull-up resistance 5 15 ? propagation delay to ovp measure time from v(vo) > v(vdac) (250mv overdrive) to v(rosc/ovp) transition to >1v. 90 180 ns ovp high voltage measure v(vccl)-v(rosc/ovp) 0 1.2 v ovp power-up high voltage rosc = 7.75 k ? . measure v(vccldrv)-v(rosc/ovp) @ 1.5v .100 .240 .375 v ovp power-up high voltage rosc = 24.5 k ? . measure v(vccldrv)-v(rosc/ovp) @ 1.5v 0 0.2 IR3502B page 7 of 38 v3.2 note 1: guaranteed by design, but not tested in production note 2: vdac output is trimmed to compensate for error amplifier input offsets errors parameter test condition min typ max unit pgood output output voltage i(pgood) = 4ma 150 300 mv leakage current v(pgood) = 5.5v 0 10 ? a under voltage threshold-vo decreasing reference to vdac -350 -300 -250 mv under voltage threshold-vo increasing reference to vdac -290 -240 -190 mv under voltage threshold hysteresis 25 60 95 mv vccl_drv activation threshold i(pg )=4ma, v(pg)<300mv, v(vccl)=0 1 2 3.6 v open sense line detection sense line detection active comparator threshold voltage 150 200 250 mv sense line detection active comparator offset voltage v(vo) < [v(vosen+) ? v(lgnd)] / 2 30 55 80 mv vosen+ open sense line comparator threshold compare to v(vccl) 87.5 90.0 92.5 % vosen- open sense line comparator threshold 0.36 0.40 0.44 v sense line detection source currents v(vo) = 100mv 200 500 700 ua vrhot comparator threshold voltage 1.584 1.600 1.616 v hotset bias current -1 0 1 ? a hysteresis 75 100 125 mv output voltage i(vrhot) = 30ma 150 400 mv vrhot leakage current v(vrhot) = 5.5v 0 10 ? a vccl regulator amplifier vccl output voltage 6.568 6.8 7.031 v vccldrv sink current 10 30 ma uvlo start threshold compare to v(vccl) 6.12 6.392 6.664 v uvlo stop threshold compare to v(vccl) 5.168 5.44 5.712 v hysteresis 0.85 0.95 1.05 v general vccl supply current 4 8 12 ma IR3502B page 8 of 38 v3.2 pin description pin# pin symbol pin description 1-8 vid7-0 inputs to vid d to a converter. 9 enable enable input. a logic low applied to this pin puts the ic into fault mode. do not float this pin as the logic state will be undefined. 10 vrhot open collector output of the vrhot co mparator which drives low if hotset pin voltage is lower than 1.6v. connect external pull-up. 11 hotset a resistor divider including thermistor senses the temperature, which is used for vrhot comparator. 12 vosen- remote sense amplifier input. connect to ground at the load. 13 vosen+ remote sense amplifier input. connect to output at the load. 14 vo remote sense amplifier output. 15 fb inverting input to the error amplifier. 16 eaout output of the error amplifier. 17 vdrp buffered, scaled and thermally compensated iin signal. connect an external rc network to fb to program converter output impedance. 18 vn node for dcr therma l compensation network. 19 vdac_buff buffered vdac. 20 vsetpt error amplifier non-inverting input. converter output voltage can be decreased from the vdac voltage with an external resist or connected between vdac and this pin (there is an internal sink current at this pin). 21 vdac regulated voltage programmed by the vi d inputs. connect an external rc network to lgnd to program dynamic vid slew rate and provide compensation for the internal buffer amplifier. 22 ss/del programs converter startup and over curr ent protection delay timing. it is also used to compensate the constant output cu rrent loop during soft start. connect an external capacitor to lgnd to program. 23 rosc/ovp connect a resistor to lgnd to program oscillator fre quency and ocset, vsetpt and vdac bias currents. oscillator frequency equals switching frequency per phase. the pin voltage is 0.6v during normal operation and higher than 1.6v if an over- voltage condition is detected. 24 lgnd local ground for internal ci rcuitry and ic substrate connection. 25 clkout clock output at switching frequency multiplied by phase number. connect to clkin pins of phase ics. 26 phsout phase clock output at switching frequ ency per phase. connect to phsin pin of the first phase ic. 27 phsin feedback input of phase clock. connect to phsout pin of the last phase ic. 28 vccl voltage regulator and ic power input. connect a decoupling capacitor to lgnd. 29 iin average current input from the phase ic(s ). this pin is also used to communicate over voltage condition to phase ics. 30 vccldrv output of the vccl regulator error am plifier to control external transistor. the pin senses 12v power supply through a resistor. 31 pgood open collector output that drives lo w during startup and under any external fault condition. indicates converter within regulation. connect external pull-up. 32 imon voltage at iout pin will be proportional to load current. IR3502B page 9 of 38 v3.2 system theory of operation system description the system consists of one control ic and a scalable ar ray of phase converters, each requiring one phase ic. the control ic communicates with the phase ics using three digi tal buses, i.e., clock, phsin, phsout and three analog buses, i.e., vdac, ea, iin. the digital buses are responsi ble for switching frequency determination and accurate phase timing control without any external component. the analog buses are used for pwm control and current sharing among interleaved phases. the control ic incorporates a ll the system functions, i.e., vid, clock signals, error amplifier, fault protections, current m onitor, etc. the phase ic implements the functions required by each phase of the converter, i.e., the gate drivers, pwm comparator and latch, over-voltage pr otection, phase disable circuit, current sensing and sharing, etc. rtherm pwm comparator off vsetpt rtcmp2 clkin rcs ccs ishare phsin dacin vcc csin+ gatel eain gateh cbst vcch csin- sw pgnd vccl rtcmp1 vid6 phsout vid6 rea off clk d q phsin psi cea off vid6 rfb + - vid6 + - + - + - + - clkin rcs + - ccs + - + - 3k rdrp gnd vout dacin vcc vdac vo lgnd ishare phsin vosns- vosns+ gatel eain gateh iin vdrp vin fb eaout clkout csin- csin+ irosc vid6 vdac remote sense amplifier vcch cbst clk r 3 d q q u246 dffrh vccl gate drive voltage phsout pwm comparator vid6 vid6 psi vid6 clk d q + - + - + - + - + - 3k vid6 clk r 3 d q q u248 dffrh vid6 + vid6 + - + body braking comparator ramp discharge clamp enable current sense amplifier rvsetpt pwm latch share adjust error amplifier reset dominant 1 2 phase ic pgnd vid6 psi - + sw vid6 + + - + thermal compensation enable ramp discharge clamp vdrp amp vdac body braking comparator vn ivsetpt clock generator pwm latch current sense amplifier imon error amplifier share adjust error amplifier reset dominant rfb1 cout control ic cfb1 1 2 psi phase ic phsout off vid6 rtcmp3 vdac_buff cea1 figure 3 system block diagram pwm control method the pwm block diagram of the xphase3 tm architecture is shown in figure 3. feed-forward voltage mode control with trailing edge modulation is used. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. input voltage is sensed in phase ics and feed-forward control is realized. the pwm ramp slope will change with the input voltage and automatically co mpensate for changes in the input voltage. the input voltage can change due to variations in the silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. frequency and phase timing control the oscillator is located in the contro l ic and the system clock frequency is programmable from 250khz to 9mhz by an external resistor. the control ic system clock signal clko ut is connected to clkin of all the phase ics. the phase timing of the phase ics is controlled by the daisy chain loop, where control ic phase clock output phsout is IR3502B page 10 of 38 v3.2 connected to the phase clock input phsin of the first pha se ic, and phsout of the first phase ic is connected to phsin of the second phase ic, etc. the phsout of the last phase ic is connected back to phsin of the control ic. during power up, the control ic sends out clock signal s from both clkout and phsout pins and detects the feedback at phsin pin to determine the phase number and monito r any fault in the daisy c hain loop. figure 4 shows the phase timing for a four phase converter. the switching fr equency is set by the resistor rosc. the clock frequency equals the number of phase times the switching frequency. phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 4 four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. with the phsin voltage high, upon receiving the falling edge of a clock pulse, the pwm latch is set. the pwmrmp voltage begins to increase; the low side driver is turned off, and the high side driver is turned on after the non-overlap time . when the pwmrmp voltage exceeds the error amplifier?s output voltage, the pwm latch is reset. th is turns off the high side driver and then turns on the low side driver after the non-overlap time. along with that, it activates the ramp discharge clamp, which quickly discharges the pwmrmp capacitor to the output voltage of share adjust amp lifier in phase ic until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. phas es can overlap and go up to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. an erro r amplifier output voltage greater than the common mode input range of the pwm comparator results in 100% duty cycl e regardless of the voltage of the pwm ramp. this arrangement guarantees the error amplifier is always in cont rol and can demand 0 to 100% duty cycle as required. it also favors response to a load step decrease which is app ropriate, given the low output to input voltage ratio of most systems. the inductor current will increase much more rapidl y than decrease in response to load transients. the error amplifier is a high speed amplifier with wide bandwidth and fast slew rate incorporated in the control ic. it is not unity gain stable. this control method is designed to provide ?single cycle tr ansient response,? where the inductor current changes in response to load transients within a single switching cy cle maximizing the effectiveness of the power train and minimizing the output capacitor requirem ents. an additional advantage of the archit ecture is that differences in the ground or input voltage at the phases have no effect on o peration since the pwm ramps are referenced to vdac. figure 5 depicts pwm operating wave forms under various conditions. IR3502B page 11 of 38 v3.2 phase ic clock pulse eain vdac pwmrmp gateh gatel steady-state operation duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vccluv, ocp, vid=11111x) figure 5 pwm operating waveforms body braking tm in a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; o min max slew v i i l t ) ( * ? ? the slew rate of the inductor current can be significantly in creased by turning off the synchronous rectifier in response to a load step decrease. the switch node voltage is t hen forced to decrease until conduction of the synchronous rectifier?s body diode occurs. this increases the vo ltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the induc tor in response to a load transient decrease is now; bodydiode o min max slew v v i i l t ? ? ? ) ( * since the voltage drop in the body diode is often comparable to the output voltage, the indu ctor current slew rate can be increased significantly. this patented technique is refe rred to as ?body braking? and is accomplished through the ?body braking comparator? located in the phase ic. if the erro r amplifier?s output voltage drops below the output voltage of the share adjust amplifier in the phase ic, this compar ator turns off the low side gate driver, enabling the bottom fet body diode to take over. there is 100mv upslope and 200mv down slope hysteresis for the body braking comparator. lossless average inductor current sensing inductor current can be sensed by connecti ng a series resistor and a capacitor netw ork in parallel with the inductor and measuring the voltage across the capacitor, as shown in figure 6. the equation of the sensing network is, cs cs l l cs cs l c c sr sl r s i c sr s v s v ? ? ? ? ? 1 ) ( 1 1 ) ( ) ( usually the resistor rcs and capacitor ccs are chosen, such that, the ti me constant of rcs and ccs equals the time constant of the inductor, which is the inductance l over the inductor dcr r l . if the two time constants match, the voltage across ccs is proportional to the current through l, and the sense circuit can be treated as if only a sense IR3502B page 12 of 38 v3.2 resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component of the inductor current. figure 6 inductor current sens ing and current sense amplifier the advantage of sensing the inductor current versus high si de or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. the output voltage can be positioned to meet a load line based on real time inform ation. except for a sense re sistor in series with the inductor, this is the only sense method that can support a single cycle transient response. other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). an additional problem associated with peak or valley curren t mode control for voltage positioning is that they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of frequency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variatio ns in inductance, current se nse amplifier bandwidth, pwm prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to- average errors. current sense amplifier a high speed differential current sense amplifier is located in the phase ic, as shown in figure 6. its gain is nominally 33 at 25oc, and the 3850 ppm/oc increase in inductor dcr should be compensated in the voltage loop feedback path. the current sense amplifier can accept positive differential input up to 50mv and negative up to -10mv before clipping. the output of the current sense amplifier is summed with the vdac voltage and sent to the control ic and other phases through an on-chip 3k ? resistor connected to the iin pin. the iin pins of all the phases are tied together and the voltage on the share bus repr esents the average current through all the indu ctors and is used by the control ic for voltage positioning and current limit protection. the input offset of this amplifier is calibrated to +/- 1mv in order to reduce the current sense error. the input offset voltage is the primary source of error for the current share loop. in orde r to achieve very small input offset error and superior current sharin g performance, the current sense amplifie r continuously calibrates itself. this calibration algorithm creates ripple on iin bus with a fr equency of fsw/(32*28) in a multiphase architecture. average current share loop current sharing between the phases of the converter is achi eved by the average current share loop in each phase ic. the output of the current sense amplifier is compared with average current at the share bus. if current in a phase is smaller than the average curre nt, the share adjust amplifier of the phase will pull down the starting point of the pwm ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the share adjust amplifier of the phase will pull up the starting poi nt of the pwm ramp thereby decreasing its duty cycle and output current. the current share amplifier is internally com pensated; such that, the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. c o l r l r c c c v o current sense amp csout i l v l v c c IR3502B page 13 of 38 v3.2 IR3502B theory of operation block diagram the block diagram of the IR3502B is shown in figure 7. vid control the control ic allows the processor voltage to be set by a parallel eight bit digital vid bus. the vid codes set the vdac as shown in table 1. the vid pins require an exte rnal bias voltage and should not be floated. the vid input comparators monitor the vid pins and control the digital- to-analog converter (dac), wh ose output is sent to the vdac buffer amplifier. the output of the buffer amplifier is the vdac pin. the vdac voltage, input offsets of error amplifier and remote sense differential amplifier are post-package trimmed to achieve 0.5% system set-point accuracy for vid range between 1v to 1.6v. a set- point accuracy of 5mv and 8mv is achieved for vid ranges of 0.8v-1v and 0.5v-0.8v respectively. the actual vdac voltage does not determine the system accuracy, which has a wider tolerance. the IR3502B can accept changes in th e vid code while operating and vary the vdac voltage accordingly. the slew rate of the voltage at the vdac pin can be adjusted by an external capacitor between vdac pin and lgnd pin. a resistor connected in series with this capacitor is requi red to compensate the vdac buffer amplifier. digital vid transitions result in a smooth analog transition of the vdac voltage and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage. adaptive voltage positioning adaptive voltage positioning is needed to optimize the outpu t voltage deviations during load transients and the power dissipation of the load at heavy load. the circuitry relate d to voltage positioning is shown in figure 8. the output voltage is set by the reference voltage vset pt at the positive input to the erro r amplifier. this reference voltage can be programmed to have a constant dc offset below t he vdac by connecting rset pt between vdac and vsetpt. the ivsetpt is controlled by the rosc. the average load current information for all the phases is fed back to the control ic throu gh the iin pin. as shown in figure 8, this information is thermally compensated with some gain by a set of buffer and thermal compensation amplifiers to generate the voltage at the vdrp pin. the v drp pin is connected to the fb pin through the resistor r drp . since the error amplifier will force the loop to mainta in fb to be equal to the vdac reference voltage, an additional current will flow into the fb pin equal to (vdrp-vdac) / r drp . when the load current increases, the vdrp voltage increases accordingly. more curr ent flows through the feedback resistor r fb and causes the output to have more droop. the positioning voltage ca n be programmed by the resistor r drp so that the droop impedance produces the desired converter output impedance. the offset and slope of the converter output im pedance are referenced to and therefore independent of the vdac voltage. inductor dcr temperature compensation a negative temperature coefficient (ntc) thermistor should be used for inductor dcr temperature compensation. the thermistor and tuning resistor network connected between the vn and vdrp pins provides a single ntc thermal compensation. the thermistor should be placed close to the pow er stage to accurately reflect the thermal performance of the inductor dcr. the resistor in series with the thermistor is used to redu ce the nonlinearity of the thermistor. remote voltage sensing vosen+ and vosen- are used for remote sensing and connected directly to the load. the remote sense differential amplifier with high speed, low input offset and low input bias current ensures accurate voltage sensing and fast transient response. there is finite input current at both pi ns vosen+ and vosen- due to the internal resistor of the differential amplifier. this limits the si ze of the resistors that can be used in series with these pins for acceptable regulation of the output voltage. IR3502B page 14 of 38 v3.2 uv 400k + - current report amp vdrp thermal comp vdac buffer amp dac_buff vdrp 200k + - dac_buf 100k vn 200k + - imon vccl 200k 200k 200k irosc vosen- vosen- disable io vccl uvlo s r q vid fault fault latch1 fault latch1 vdac vdac vccl uvlo vid fault latch fault latch2 1.17v ov fault ov@operation vo ov@operation ov@start vccl uvlo reset ov@start oc after vrrdy vccl uvlo ss reset open sense line vccl uvlo open daisy chain oc before vrrdy ov fault eaout ss reset open voltage loop vccl + - + s r q + - + - + - 25k + - + - + - + - s r q + - + - 25k s r q 25k + - + - + - + - + - + - + - s r q + - + - 25k + - + - s r q vid2 vid4 + - vid3 s r q vid7 vid6 pgood ss/del vid5 phsout clkout vid0 vid1 enable vo vccldrv vrhot hotset vccl phsin eaout vdac vosen- vosen+ uv iin vsetpt fb dac_buf vccl vccl vid4 vid5 vid6 vid7 vid1 vid2 vid3 1.03 0 vid6 vid7 vid0 vid2 vid3 vid4 vid5 phsin vboot vid0 vid1 vidsel vidsel phsout irosc irosc disable ivosen- vidsel phsout clkout fault irosc + - f_vdac vid0 dis ss cleared fault latch1 vid input comparators (1/8 shown) oc ss reset error amplifier delay comparator set dominant 4.0v 800mv enable comparator digital to analog converter 1.3us blanking 850mv vboot (1.1v) vdac buffer amplifier internal vdac vdrp dac_buf set dominant vboot latch vccl regulator amplifier over voltage comparator vid sample delay comparator 250ns blanking vdrp vccl output comparator isource remote sense amplifier 6.8v vrhot comparator current source generator oc delay counter reset dominant power ok latch isink vid fault latch intel 0.2v discharge comparator 80mv 120mv 1.6v 50mv dynamic vid vid fault set dominant ivosen- ivosen+ 200mv 1.21v power-up ov comparator 0.4v dynamic vid detect comparator 6.1v + - soft start clamp isetpt uv cleared fault latch2 set dominant oc limit comparator 1.4v open sense line detect comparators 60mv 130mv 3mv 4.5ua 3v open sense line 0.6v open daisy chain vccldrv-0.2v oc limit amplifier idchg open sense line detect comparators detection pulse detection pulse 8-pulse delay 1.08v set dominant ov fault latch 1.6v 1.5v ov@operation + - rosc/ovp 0.6v lgnd rosc buffer amplifier vccldrv ov@start vdac vo vccldrv 6.45v 5.45v 315mv 275mv ov fault hold last vid fault latch1 fault latch2 figure 7 block diagram IR3502B page 15 of 38 v3.2 table 1 vr11 vid table (part1) hex (vid7:vid0) dec (vid7:vid0) voltage hex (vid7:vid0) dec (vid7:vid0) voltage 00 00000000 fault 40 01000000 1.21250 01 00000001 fault 41 01000001 1.20625 02 00000010 1.60000 42 01000010 1.20000 03 00000011 1.59375 43 01000011 1.19375 04 00000100 1.58750 44 01000100 1.18750 05 00000101 1.58125 45 01000101 1.18125 06 00000110 1.57500 46 01000110 1.17500 07 00000111 1.56875 47 01000111 1.16875 08 00001000 1.56250 48 01001000 1.16250 09 00001001 1.55625 49 01001001 1.15625 0a 00001010 1.55000 4a 01001010 1.15000 0b 00001011 1.54375 4b 01001011 1.14375 0c 00001100 1.53750 4c 01001100 1.13750 0d 00001101 1.53125 4d 01001101 1.13125 0e 00001110 1.52500 4e 01001110 1.12500 0f 00001111 1.51875 4f 01001111 1.11875 10 00010000 1.51250 50 01010000 1.11250 11 00010001 1.50625 51 01010001 1.10625 12 00010010 1.50000 52 01010010 1.10000 13 00010011 1.49375 53 01010011 1.09375 14 00010100 1.48750 54 01010100 1.08750 15 00010101 1.48125 55 01010101 1.08125 16 00010110 1.47500 56 01010110 1.07500 17 00010111 1.46875 57 01010111 1.06875 18 00011000 1.46250 58 01011000 1.06250 19 00011001 1.45625 59 01011001 1.05625 1a 00011010 1.45000 5a 01011010 1.05000 1b 00011011 1.44375 5b 01011011 1.04375 1c 00011100 1.43750 5c 01011100 1.03750 1d 00011101 1.43125 5d 01011101 1.03125 1e 00011110 1.42500 5e 01011110 1.02500 1f 00011111 1.41875 5f 01011111 1.01875 20 00100000 1.41250 60 01100000 1.01250 21 00100001 1.40625 61 01100001 1.00625 22 00100010 1.40000 62 01100010 1.00000 23 00100011 1.39375 63 01100011 0.99375 24 00100100 1.38750 64 01100100 0.98750 25 00100101 1.38125 65 01100101 0.98125 26 00100110 1.37500 66 01100110 0.97500 27 00100111 1.36875 67 01100111 0.96875 28 00101000 1.36250 68 01101000 0.96250 29 00101001 1.35625 69 01101001 0.95625 2a 00101010 1.35000 6a 01101010 0.95000 2b 00101011 1.34375 6b 01101011 0.94375 2c 00101100 1.33750 6c 01101100 0.93750 2d 00101101 1.33125 6d 01101101 0.93125 2e 00101110 1.32500 6e 01101110 0.92500 2f 00101111 1.31875 6f 01101111 0.91875 30 00110000 1.31250 70 01110000 0.91250 31 00110001 1.30625 71 01110001 0.90625 32 00110010 1.30000 72 01110010 0.90000 33 00110011 1.29375 73 01110011 0.89375 34 00110100 1.28750 74 01110100 0.88750 35 00110101 1.28125 75 01110101 0.88125 36 00110110 1.27500 76 01110110 0.87500 37 00110111 1.26875 77 01110111 0.86875 38 00111000 1.26250 78 01111000 0.86250 39 00111001 1.25625 79 01111001 0.85625 3a 00111010 1.25000 7a 01111010 0.85000 3b 00111011 1.24375 7b 01111011 0.84375 3c 00111100 1.23750 7c 01111100 0.83750 3d 00111101 1.23125 7d 01111101 0.83125 3e 00111110 1.22500 7e 01111110 0.82500 3f 00111111 1.21875 7f 01111111 0.81875 IR3502B page 16 of 38 v3.2 table 1 vr11 vid table (part 2) hex (vid7:vid0) dec (vid7:vid0) voltage hex (vid7:vid0) dec (vid7:vid0) voltage 80 10000000 0.81250 c0 11000000 n/a 81 10000001 0.80625 c1 11000001 n/a 82 10000010 0.80000 c2 11000010 n/a 83 10000011 0.79375 c3 11000011 n/a 84 10000100 0.78750 c4 11000100 n/a 85 10000101 0.78125 c5 11000101 n/a 86 10000110 0.77500 c6 11000110 n/a 87 10000111 0.76875 c7 11000111 n/a 88 10001000 0.76250 c8 11001000 n/a 89 10001001 0.75625 c9 11001001 n/a 8a 10001010 0.75000 ca 11001010 n/a 8b 10001011 0.74375 cb 11001011 n/a 8c 10001100 0.73750 cc 11001100 n/a 8d 10001101 0.73125 cd 11001101 n/a 8e 10001110 0.72500 ce 11001110 n/a 8f 10001111 0.71875 cf 11001111 n/a 90 10010000 0.71250 d0 11010000 n/a 91 10010001 0.70625 d1 11010001 n/a 92 10010010 0.70000 d2 11010010 n/a 93 10010011 0.69375 d3 11010011 n/a 94 10010100 0.68750 d4 11010100 n/a 95 10010101 0.68125 d5 11010101 n/a 96 10010110 0.67500 d6 11010110 n/a 97 10010111 0.66875 d7 11010111 n/a 98 10011000 0.66250 d8 11011000 n/a 99 10011001 0.65625 d9 11011001 n/a 9a 10011010 0.65000 da 11011010 n/a 9b 10011011 0.64375 db 11011011 n/a 9c 10011100 0.63750 dc 11011100 n/a 9d 10011101 0.63125 dd 11011101 n/a 9e 10011110 0.62500 de 11011110 n/a 9f 10011111 0.61875 df 11011111 n/a a0 10100000 0.61250 e0 11100000 n/a a1 10100001 0.60625 e1 11100001 n/a a2 10100010 0.60000 e2 11100010 n/a a3 10100011 0.59375 e3 11100011 n/a a4 10100100 0.58750 e4 11100100 n/a a5 10100101 0.58125 e5 11100101 n/a a6 10100110 0.57500 e6 11100110 n/a a7 10100111 0.56875 e7 11100111 n/a a8 10101000 0.56250 e8 11101000 n/a a9 10101001 0.55625 e9 11101001 n/a aa 10101010 0.55000 ea 11101010 n/a ab 10101011 0.54375 eb 11101011 n/a ac 10101100 0.53750 ec 11101100 n/a ad 10101101 0.53125 ed 11101101 n/a ae 10101110 0.52500 ee 11101110 n/a af 10101111 0.51875 ef 11101111 n/a b0 10110000 0.51250 f0 11110000 n/a b1 10110001 0.50625 f1 11110001 n/a b2 10110010 0.50000 f2 11110010 n/a b3 10110011 n/a f3 11110011 n/a b4 10110100 n/a f4 11110100 n/a b5 10110101 n/a f5 11110101 n/a b6 10110110 n/a f6 11110110 n/a b7 10110111 n/a f7 11110111 n/a b8 10111000 n/a f8 11111000 n/a b9 10111001 n/a f9 11111001 n/a ba 10111010 n/a fa 11111010 n/a bb 10111011 n/a fb 11111011 n/a bc 10111100 n/a fc 11111100 n/a bd 10111101 n/a fd 11111101 n/a be 10111110 n/a fe 11111110 fault bf 10111111 n/a ff 11111111 fault IR3502B page 17 of 38 v3.2 current sense amplifier phase ic + - phase ic current sense amplifier 3k csin+ iout csin- vdac + - 3k vdac vsetpt csin+ csin- iout eaout vdac error amplifier thermal comp amplifier vdac buffer remote sense amplifier fb rtherm rtcmp2 rtcmp1 vdrp + - dac_buff vn 200k rtcmp3 100k + - + - rfb + - rdrp vosen- vosen+ vdac vo iin control ic figure 8 adaptive voltage positioning with thermal compensation. start-up sequence the IR3502B has a programmable soft-start function to lim it the surge current during the converter start-up. a capacitor connected between the ss/del and lgnd pins cont rols soft start timing, over-current protection delay and hiccup mode timing. a charge current of 52.5ua and disc harge current of 4ua control the up slope and down slope of the voltage at the ss/del pin respectively. figure 9 depicts start-up sequence of converter with vr 11.1 vid. if there is no fault, as the enabl e is asserted, the ss/del pin will start charging. the error amplifier output eaout is clamped low until ss/del reaches 1.4v. the er ror amplifier will then regulate the converter?s output voltage to match the ss/del voltage less the 1.4v offset unt il the converter output reache s the 1.1v boot voltage. the ss/del voltage continues to increase until it rises above the 3.0v thres hold of vid delay comparator. the vid set inputs are then activated and vdac pin transitions to the level determined by the vid inputs. the ss/del voltage continues to increase until it rises above 3.92v and allows the pgood signal to be asserted. ss/del finally settles at 4.0v, indicating the end of the soft start. the re mote sense amplifier has a very low operating range of 50 mv in order to achieve a smooth soft start of output voltage without bump. the vccl under voltage lock-out, vid fault modes, over current, as well as a low signal on the enable input immediately sets the fault latch, which causes the eaout pin to drive low turning off the phase ic drivers. the pgood pin also drives low and ss/del begin to discharge until the voltage reaches 0.2v. if the fault has cleared the fault latch will be reset by t he discharge comparator allowing a normal soft start to occur. other fault conditions, such as over voltage, open sense lines, open loop monitor, and open daisy chain, set different fault latches, which start discharging ss/del, pull down eaout voltage and drive pgood low. however, the latches can only be reset by cycling vccl power. IR3502B page 18 of 38 v3.2 soft start time (td2) td5 vrrdy 3.92v ss/del (12v) start delay (td1) vcc enable 1.4v vout 4.0v vid sample time (td3) vdac normal operation 3v td4 vrrdy delay time (td4+td5) 1.1v vid eaout figure 9 start-up sequence of converter with boot voltage current monitor (imon) the control ic generates a current monitor signal imon using the vdrp voltage and the vdac reference, as shown in figure 10. this voltage is thermally compensated for the inductor dcr variation. the voltage at this pin reports the average load current information without being referenced to vdac. the slope of the imon signal with respect to the load current can be adjusted with the resistors rtcmp2 and rtcmp3. the imon signal is clamped at 1.03v in order to facilitate di rect interfacing with the cpu. + - vdrp 200k vdrp buffer + - iin 200k vosen- 200k 200k 200k 100k 0 1.03 imon dac_buff dac_buff from phase ics rtcmp3 control ic vdac vdac buffer thermal comp amplifier rtherm vdrp rtcmp2 vn rtcmp1 + - + - figure 10 current report signal (imon) implementation IR3502B page 19 of 38 v3.2 constant over-current control during soft start the over current limit is fixed by 1.17v above the vdac. if the vdrp pin vo ltage, which is proportional to the average current plus vdac voltage, ex ceeds (vdac+1.17v) during soft start, t he constant over-current control is activated. figure 11 shows the constant over-current control with delay during soft start. the delay time is set by the rosc resistor, which sets the number of switching cycles for the delay counter. the delay is required since over- current conditions can occur as part of normal operation due to inrush current. if an over-current occurs during soft start (before pgood is assert ed), the ss/del voltage is regulated by the over current amplifier to limit the output current below the threshold set by oc lim it voltage. if the over-current conditi on persists after delay time is reached, the fault latch will be set pulling the error amplifier?s ou tput low and inhibiting switch ing in the phase ics. the ss/del capacitor will discharge unt il it reaches 0.2v and the fault latch is re set allowing a normal soft start to occur. if an over-current condition is again en countered during the soft start cycle, the constant over-current control actions will repeat and the converter will be in hiccup mode. the delay time is controlled by a counter which is triggered by clock. the counter values vary with switching frequency per phase in order to have a similar delay time for different switching frequencies. over-current protection (output shorted) normal operation 3.88v ea hiccup over-current protection (output shorted) power-down ocp delay start-up with output shorted normal operation 3.92v ss/del iout vout vrrdy 1.1v enable ocp threshold =vdac_buff+1.17v 4.0v normal start-up (output shorted) normal start-up internal oc delay figure 11 constant over-current cont rol waveforms during and after soft start. over-current hiccup protection after soft start the over current limit is fixed at 1. 17v above the vdac. figure 11 shows the constant over-current control with delay after pgood is asserted. the del ay is required since over-current co nditions can occur as part of normal operation due to load transients or vid transitions. if the vdrp pin voltage, which is proportional to the average current plus vdac vo ltage, exceeds (vdac+1.17v) after pgood is asserted, it will initiate the discharge of the capacitor at ss/del. t he magnitude of the discharge current is proportional to the voltage difference between vdrp and (vda c+1.17v) and has a maximum nominal value of 55ua. if the over-current condition persists l ong enough for the ss/del capacitor to discharge below the 120mv offset of the delay comparator, the fault latch will be set pulling the error amplifier? s output low and inhibiting switching in the phase ics and de-asserting the pgood si gnal. the output current is not controlled during the delay time. the ss/del capacitor will discharge until it reaches 200 mv and the fault latch is reset allowing a normal soft IR3502B page 20 of 38 v3.2 start to occur. if an over-current condition is again encount ered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode. linear regulator output (vccl) the IR3502B has a built-in linear regulator controller, and only an external npn transistor is needed to create a linear regulator. the voltage of vccl is fixed at 6.8v wi th the feedback resistive divider internal to the ic. the regulator output powers the gate drivers of the phase ics and circuits in the c ontrol ic, and the voltage is usually programmed to optimize the converter efficiency. the linear regulator can be compensated by a 4.7uf capacitor at the vccl pin. as with any linear regulator, due to stability reasons, there is an upper limit to the maximum value of capacitor that can be used at this pin and it?s a function of the number of phases used in the multiphase architecture and their switching frequency. figure 12 shows the stability plots for the linear regulator with 5 phases switching at 750 khz. vccl under voltage lockout (uvlo) the IR3502B has no under voltage lockout for converter input voltage (vcc), but monitors the vccl voltage instead, which is used for the gate dr ivers of phase ics and circuits in cont rol ic and phase ics. during power up, the fault latch will be reset if vccl is above 94% of 6.8v. if vccl voltage drops below 80% of 6.8v, the fault latch will be set. figure 12 vccl regulator stability with 5 phases and phsout equals 750 khz. over voltage protection (ovp) output over-voltage happens during normal operation if a high side mosfet short oc curs or if output voltage is out of regulation. the over-voltage protection comparator moni tors vo pin voltage. if vo pin voltage exceeds vdac by 130mv after ss, as shown in figure 13, IR3502B raises rosc/ovp pin voltage above to v(vccl) - 1v, which sends over voltage signal to system. during startup, the th reshold is 130 mv above last vid and reverts back to vboot+130mv during boot mode. the rosc/ovp pin can also be connected to a thyrister in a crowbar circuit, which pulls the converter input low in over voltage condition s. the over voltage condition also sets the over voltage fault latch, which pulls error amplifier output low to turn off the converter output. at the same time iin pin (iin of phase ics) is pulled up to vccl to communicate the over voltage condition to phase ics, as shown in figure 13. in each phase ic, the ovp circuit overrides the normal pwm operat ion and will fully turn-on the low side mosfet within approximately 150ns. the low side mosfet will remain on until iin pin voltage drops below v(vccl) - 800mv, which signals the end of over voltage condition. an over volt age fault condition is latched in the IR3502B and can only be cleared by cycling power to the IR3502B vccl. IR3502B page 21 of 38 v3.2 after ovp 130mv fault latch output voltage (vo) ovp threshold iin (ishare) vccl-800 mv ovp condition normal operation gateh (phase ic) gatel (phase ic) error amplifier output (eaout) vdac figure 13 over-voltage protection during normal operation vccl+0.7v vccl+0.7v 12v rosc/ovp output voltage (vosen+) vccldrv vccl uvlo 1.6v 12v vcc 1.8v figure 14 over-voltage prot ection during power-up. IR3502B page 22 of 38 v3.2 rosc/ovp output voltage (vosen+) 1.8v 1.6v vccldrv vccl uvlo vcc 12v vccl+0.7v vccl+0.7v 1.73v figure 15 over-voltage protection with pr e-charging converter output vo > 1.73v vid + 0.13v vccl - 1v ss/del 3.92v (4v-0.08v) rosc/ovp output voltage (vosen+) vccl+0.7v vccl+0.7v 0.6v vccldrv vccl uvlo 1.73v vcc 12v figure 16 over-voltage protection with pre-char ging converter output vid + 0.13v IR3502B page 24 of 38 v3.2 is set. a high level at the pgood pin indicates that t he converter is in operation and has no fault. the pgood stays high as long as the output voltage is within 300 mv of the programmed vi d. during start-up, it is pulled low with an input voltage as low as 2 v. it stays low until the startup sequence has comp leted, and the output voltage has moved to the programmed vid. open voltage loop detection the output voltage range of error amplifier is detected all the time to ensure the voltage loop is in regulation. if any fault condition forces the error amplifier output above vccl-1 .08v for 8 switching cycles, the fault latch is set. the fault latch can only be cleared by cycling power to vccl. open remote sense line protection if either remote sense line vosen+ or vosen- or both are open, the output of remote sense amplifier (vo) drops. the IR3502B monitors vo pin voltage continuously. if vo voltage is lower than 200 mv, two separate pulse currents are applied to vosen+ and vosen- pins respectively to check if the sense lines are open. if vosen+ is open, a voltage higher than 90% of v(vccl) will be pr esent at vosen+ pin and the output of open line detect comparator will be high. if vosen- is open, a voltage higher than 700mv will be present at vosen- pin and the output of open-line-detect comparator will be high. the open sense line fault latc h is set, which pulls error amplifier output low immediately and shut down the converter. the ss/del voltage is discharged and the fault latch can only be reset by cycling vccl power. duri ng dynamic vid down, ovp may be tri ggered when output voltage can not follow vdac voltage change at light load with large output capacitance. therefore, ove r-voltage threshold is raised to 1.73v from vdac+130mv whenever dynamic vid is detected and the difference between output voltage and vdac is more than 50mv, as shown in figure 17. the ov er-voltage threshold is changed back to vdac+130mv if the difference is smaller than 50mv. open daisy chain protection IR3502B checks the daisy chain every time it powers up. it starts a daisy chain pulse on the phsout pin and detects the feedback at phsin pin. if no pulse comes back after 32 clkout pulse s, the pulse is restarted again. if the pulse fails to come back the second time, the open daisy chain fault is registered, and ss/del is not allowed to charge. the fault latch can only be reset by cycling the power to vccl. after powering up, the IR3502B monitors phsin pin for a phase input pulse equal or less than the number of phases detected. if phsin pulse does not return within the number of phases in the converter, another pulse is started on phsout pin. if the second started phsout pul se does not return on phsin, an open daisy chain fault is registered. enable input the enable pin below 0.8v sets the fault latch and a volt age above 0.85v enables the soft start of the converter. thermal monitoring (vrhot) a resistor divider including a thermistor at hotset pin se ts the vrhot threshold. the thermistor is usually placed at the temperature sensitive region of the converter, and is linearized by a series resistor. the IR3502B compare hotset pin voltage with a reference voltage of 1.6v. the vrhot pin is an open-collector output and should be pulled up to a voltage source through a resistor. if the t hermal trip point is reached the vrhot output drives low. the hysteresis of the vrhot comparator helps eliminate toggling of vrhot output. the overall system must be considered when designing for o vp. in many cases the over -current protection of the ac-dc or dc-dc converter su pplying the multiphase converter will be tr iggered and provide e ffective protection without damage as long as all pcb traces and components are sized to handle the worst-case maximum current. if this is not possible, a fuse can be added in t he input supply to the multiphase converter. IR3502B page 25 of 38 v3.2 phase number determination after a daisy chain pulse is started, the IR3502B checks the timing of the input pulse at phsin pin to determine the phase number. this information is used to have symmetr ical phase delay between phase switching without the need of any external component. single phase operation in an architecture where only a single phase is needed the switching frequency is determined by the clock frequency. current share loop compensation the internal compensation of current share loop ensures t hat crossover frequency of the current share loop is at least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated. the crossover frequency of current share loop is approximately 8 khz. fault operation table the fault table below describes the different faults that can occur and how ir3502a would react to protect the supply and the load from possible damage. the fault types t hat can occur are listed in row 1. row 2 has the method that a fault is cleared. the first 5 faults are latched in the uv fault latch and the vccl power has to be recycled by switching off the input and switching it back on for the conver ter to work again. the rest of the faults (except for uvlo vout) are latched in the ss fault latch and does not need to recycle the vccl power in order to resume normal operation once the fault condition clears. most of the faults disable the error amplifier (ea) and discharge the soft start capacitor. all the faults flag pgood. pgood retu rns back to high when the faults are cleared. the delay row shows reaction time after detecting a fault condition. de lays are provided to minimize the possibility of nuisance faults. fault type open daisy open control loop open sense line over voltage vid disable vccl uvlo oc before start-up oc after start-up vout uvlo fault clearing method recycle vccl resume normal operation when condition clears error amp disabled yes no rosc/ovp & iin drive high until ov clears no yes no ss/del discharge yes no flags pgood yes delay? 32 clock pulses 8 phsout pulses no no 1.3us blank time 250 ns blank time no phsout pulses. count programmed by rosc value ss/del discharge threshold no IR3502B page 26 of 38 v3.2 design procedures - IR3502B and ir3507 chipset IR3502B external components oscillator resistor rosc the oscillator of IR3502B generates square-wave pulses to synchronize the phase ics. the switching frequency of the each phase converter equals the phsout fre quency, which is set by the external resistor r osc according to the curve in figure 18. the clkout frequency equals the switching frequency multiplied by the phase number. the rosc sets the reference current used for no load offset which is given by figure 19 and equals: rosc isetpt 595 . 0 ? (1) soft start capacitor c ss/del the soft start capacitor c ss/del programs five different time parameters . they include soft start delay time, soft start time, vid sample delay time, vr ready delay time and over-current fault latch delay time after vr ready. for the converter using vid with boot voltage, the ss/del pin voltage controls the slew rate of the converter output voltage, as shown in figure 9. after the enable pin voltage rises above 0.85v, there is a soft-start delay time td1 , after which the error amplifier output is released to allow the soft start of output voltage. the soft start time td2 represents the time during which converter voltage rises from zero to 1.1v . the vid sample delay time (td3) is the time period when vid stays at boot voltage of 1.1v. vid rise or fall time (td4) is the time when vid changes from boot voltage to the final voltage. the vr ready delay time (td5) is the time period from vr reaching the final voltage to the vr ready signal being issued, which is determined by the delay comparator threshold. c ss/del = 0.1uf meets all the specifications of td1 to td 5, which are determined by (2) to (6) respectively. 6 / / 10 * 5 . 52 4 . 1 * 4 . 1 * 1 ? ? ? del ss chg del ss c i c td (2) 6 / / 10 * 5 . 52 1 . 1 * 1 . 1 * 2 ? ? ? del ss chg del ss c i c td (3) 6 / / 10 * 5 . 52 7 . 0 * ) 1 . 1 4 . 1 3 ( * 3 ? ? ? ? ? del ss chg del ss c i c td (4) 6 / / 10 * 5 . 52 1 . 1 * 1 . 1 * 4 ? ? ? ? ? dac del ss chg dac del ss v c i v c td (5) 4 10 * 5 . 52 92 . 0 * 4 ) 3 92 . 3 ( * 5 6 / / td c td i c td del ss chg del ss ? ? ? ? ? ? (6) IR3502B page 27 of 38 v3.2 o o chg del ss v td v i td c 6 / 10 * 5 . 52 * 2 * 2 ? ? ? (7) the soft start delay time (td1) and vr ready delay time (td3) are determined by (8) to (9) respectively. 6 / / 10 * 5 . 52 4 . 1 * 4 . 1 * 1 ? ? ? del ss chg del ss c i c td (8) 6 / / 10 * 5 . 52 ) 0 . 4 ( * ) 0 . 4 ( * 3 ? ? ? ? ? o del ss chg o del ss v c i v c td (9) once c ss/del is chosen, the minimum over-current fault latch delay time t ocdel is fixed and can be quantified as 6 / / 10 * 55 12 . 0 * 12 . 0 * ? ? ? del ss dischg del ss ocdel c i c t (10) vdac slew rate programming capacitor c vdac and resistor r vdac the slew rate of vdac slope sr down can be programmed by the external capacitor c vdac as defined in (11), where i sink is the sink current of vdac pin. the slew rate of vdac up-slope is the same as that of down-slope. the resistor r vdac is used to compensate vdac circ uit and can be calculated as follows down down sink vdac sr sr i c 6 10 * 44 ? ? ? (11) vdac vdac c khz r ? ? ? ? 900 2 1 ? (12) current report gain and thermal compensation intel vr11.1 specifications require imon to report the co re maximum load current of the cpu be reported as 1 v nominal. the core maximum current can be different for different platforms. the imon tuning resistors can therefore be adjusted and thermally compensated to adjust the load current gain with respect to the imon. the expressions that govern the relationship between load current, imon, and vdrp at room temperature are given by o cs room l i rtcmp room rtherm rtcmp ii rtcmp n g r vdac vdrp ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3 ) _ 1 ( ) 2 ( 1 3 1 _ (13) o cs room l i rtcmp room rtherm rtcmp ii rtcmp n g r imon ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3 ) _ 1 ( ) 2 ( 1 3 1 _ (14) the change in inductor dcr with temperature is compen sated by an equivalent variation in the rtherm. the following equations derive the rtcmp1 and rtcmp2 if rtcmp3 and the thermistor (rtherm and therm ) are fixed. )] ( 10 * 3850 1 [ _ 6 _ _ room max l room l max l t t r r ? ? ? ? ? ? (15) max _ 1 o room therm i v k ? , n g r k cs room l room c ) ( _ _ ? ? , n g r k cs l t c ) ( max _ max _ ? ? (16) IR3502B page 28 of 38 v3.2 3 1 3 _ _ _ rtcmp k k r room c room therm room t ? ? ? ? ? ? ? ? ? ? ? ? (17) 3 1 3 max _ _ max _ rtcmp k k r t c room therm t t ? ? ? ? ? ? ? ? ? ? ? ? (18) ? ? ? ? ? ? ? ? ? ? ? ? ? ? room therm t t room t e rtherm rtherm 273 1 273 1 max max ? (19) max t room th rtherm rtherm b ? ? (20) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? room t t t t room t room th r r rtherm rtherm rtherm rtherm c _ max _ max max 1 1 (21) ?? 2 4 1 2 th th th c b b rtcmp ? ? ? ? ? (22) ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 2 max _ max _ rtcmp r r rtcmp t t t t (23) droop resistor the inductor dc resistance is utilized to sense the inductor current. the copper wire of inductor has a constant temperature coefficient of 3850 ppm/c , and therefore the maximum inductor dcr can be calculated from (15), where r l_tmax and r l_room are the inductor dcr at maximum temperature t max and room temperature t room . respectively. after the thermal compensation is achiev ed using the procedure given above, the droop resistance can be calculated using the following equation. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3 1 3 1 _ _ rtcmp r n r g r r r room t room l cs o fb drp (24) over-current threshold once the current report gain and the thermal compensation are calculated the ocp threshold is calculated using the following expression. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 3 ) _ 1 ( ) 2 ( 1 3 1 17 . 1 _ rtcmp room rtherm rtcmp ii rtcmp n g r i cs room l ocp (25) no load output voltage setting resistor r vsetpt , a resistor between vsetpt pin and vdac is used to create output voltage offset v o_nlofst, which is the difference between v dac voltage and output voltage at no load condition. r vsetpt is determined by (26), where i vsetpt is the current flowing out of vsetpt pin as shown in figure 19. vsetpt nlofst o vsetpt i v r _ ? (26) IR3502B page 29 of 38 v3.2 thermistor r hotset3 and over temperature setting resistors r hotset1 and r hotset2 the threshold voltage of vrhot comparator is fixed at 1.6v, and a negative temperature coefficient (ntc) thermistor r hotset3 is required to sense the temperature of the power stage. if we pre-select r hotset3 , the ntc thermistor resistance at allowed maximum temperature t max is calculated from (27). )] 1 1 ( * [ * _ _ 3 3 room max l hotset hotset tmax t t b exp r r ? ? (27) select the series resistor r hotset2 to linearize the ntc thermistor, which has non-linear characteristics in the operational temperature range. then calculate r hotset1 corresponding to the allowed maximum temperature tmax from (28). 6 . 1 ) 6 . 1 ( * ) ( 2 1 ? ? ? vccl r r r hotset tmax hotset (28) vccl capacitor c vccl the capacitor is selected based on the stability requirem ent of the linear regulator and the load current to be driven. the linear regulator supplies the bias and gate dr ive current of the phase ics. a 4.7uf normally ensures stable vccl performance for intel vr11.1 applications. vccl regulator drive resistor r vccldrv the drive resistor is primarily dependent on the lo ad current requirement of the linear regulator and the minimum input voltage requirements. the following equation gives an estimate of the average load current of the switching phase ics. ? ? n ma f q q i sw gt gb avg drive ? ? ? ? ? 10 ) ( _ (29) q gb and q gt are the gate charge of the top and bottom fet. for a minimum input voltage and a maximum vccl, the maximum r vccldrv required to use the full pull-down curre nt of the vccl driver is given by min _ / 8 . 6 7 . 0 (min) ? avg drive i vccldrv i v v r ? ? ? (30) due to limited pull down capability of the vccldrv pin, make sure the following condition is satisfied. ma r v v vccldrv i 10 8 . 6 7 . 0 (max) ? ? ? (31) in the above equation, v i ( min) and v i ( max) is the minimum and maximum anticipated input voltage. if the above condition is not satisfied there is a need to use a device with higher min or darlington configuration can be used instead of a single npn transistor. current monitor filter a filter is added to isolate the cpu from rapid changes in the load current and trigger false response. a filter with 300 us time constant provides adequate delay for intel vr11.1 response. a 1k resistor between imon and local ground helps equalize the source and sink current of the imon pin. IR3502B page 30 of 38 v3.2 design example ? high fr equency converter (fig. 20) specifications input voltage: v i =12 v dac voltage: v dac =1.2 v no load output voltage offset: v o_nlofst =10 mv continuous output current: i otdc =110 a maximum dc output current: i omax =140 a current report gain =0.95 v represents i omax output impedance: r o =0.8 m ? soft start delay time: td1=0-5ms soft start time: td2=0.05ms-10ms vid sample delay time: td3=0.05-3ms vid rise time: td4=0-3.5ms vr ready delay time: td5=0.05ms-3ms maximum over current delay time: t ocdel <2.5ms dynamic vid up-slope slew rate: sr up =10mv/us over temperature threshold: t max =100 oc power stage phase number: n=5 switching frequency: f sw = 700 khz output inductors: l=70 nh, r l =0.35 m ? (including solder resistance) output capacitors: cera mic: c=22uf, number n c =50 sp: c=220uf, number n sp =2 IR3502B external components oscillator resistor rosc once the switching frequency is chosen, r osc can be determined from the curve in figure 18 of this data sheet. for a switching frequency of 700khz per phase, choose r osc = 17.4 k ? . the reference current is given by 30ua. soft start capacitor c ss/del determine the soft start capacitor to meet the specifications of the delay time. choose c ss/del =0.1uf. the soft start delay time is ms i c td chg del ss 67 . 2 10 * 5 . 52 4 . 1 * 10 * 1 . 0 4 . 1 * 1 6 6 / ? ? ? ? ? the soft start time is ms i c td chg del ss 1 . 2 10 * 5 . 52 1 . 1 * 10 * 1 . 0 1 . 1 * 2 6 6 / ? ? ? ? ? the vid sample delay time is ms i c td chg del ss 33 . 1 10 * 5 . 52 7 . 0 * 10 * 1 . 0 ) 1 . 1 4 . 1 2 . 3 ( * 3 6 6 / ? ? ? ? ? ? ? vid rise time is IR3502B page 31 of 38 v3.2 ms i v c td chg dac del ss 38 . 0 10 * 5 . 52 1 . 1 3 . 1 * 10 * 1 . 0 1 . 1 * 4 6 6 / ? ? ? ? ? ? ? the vr ready delay time is ms td td i c td chg del ss 37 . 1 4 10 * 5 . 52 92 . 0 * 10 * 1 . 0 4 ) 3 92 . 3 ( * 5 6 6 / ? ? ? ? ? ? ? ? minimum over current fault latch delay time is ms i c t ocdischg del ss ocdel 21 . 0 10 * 55 12 . 0 * 10 * 1 . 0 12 . 0 * 6 6 / ? ? ? ? ? vdac slew rate programming capacitor c vdac and resistor r vdac calculate the vdac down-slope slew-rate programming ca pacitor from the required down-slope slew rate. the up-slope slew rate is the same as the down-slope slew rate. nf sr i c down sink vdac 4 . 4 10 / 10 * 10 10 * 44 6 3 6 ? ? ? ? ? ? a 3.3 nf capacitor can be used. a series resi stor is used to stabiliz e the vdac buffer. ? ? ? ? ? ? 53 900 2 1 vdac vdac c khz r ? a 50 ? resistor is selected. no load output voltage setting resistor r vsetpt from figure 19, the bias current of vsetpt pin is 30 ua with r osc =17.4 k ? . ? ? ? ? ? ? 330 10 * 30 10 * 10 6 3 _ vsetpt nlofst o vsetpt i v r current report gain and thermal compensation the reporting gain specifies the max load current in form of a voltage. for this exampl e, the 140 a represents 0.95 v at imon. if the thermal effects are neglected (14) can be used to find the reporting gain. however, as the inductor dcr increases with temperature, t he thermal compensation string (rtcmp 1, rtcmp2, and rtherm) can be used to compensate this change in dcr. assuming t room =25 deg, t max =100 deg the change in dcr is found our using (15) ? ? ? ? ? ? ? ? m m r max l 45 . 0 )] 25 100 ( 10 * 3850 1 [ 35 . 0 6 _ preselect rtcmp3=1 k ? , and r therm_room =10 k ? with therm =3380k rtcmp1 and rtcmp2 can be found out using (16)-(23) rtcmp1=8.837 k ? rtcmp2=8.457 k ? IR3502B page 32 of 38 v3.2 droop resistor based on the above calculation r drp can be selected to obtain specific output impedance. pre-select r fb =1 k ? and using r o =0.8 m ? , g cs =33.5 along with the converter parameters can be plugged into (24) to find out r drp . ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? k k k m m k r drp 5 . 7 1 618 . 5 1 5 35 . 0 5 . 33 8 . 0 1 3 1 over current threshold the ocp is fixed at 1.17 v above the vdac voltag e. therefore, it can be determined as follows a k k k ii k m i ocp 182 1 ) 10 837 . 8 ( ) 457 . 8 ( 1 5 5 . 33 35 . 0 3 1 17 . 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? vccl drive resistor r vccldrv the maximum drive current for the linear regulator is dependent on the type of mosfet used. for this example, it?s assumed that ir6622 and irf6628 are us ed as the control and sync fet respectively. ?? ma ma k n n i avg drive 195 5 10 700 ) 11 3 . 30 ( _ ? ? ? ? ? ? the minimum input voltage is assumed to be 10.5 v and vccl is fixed at 6.5v for this design. ? ? ? ? ? 700 30 / 195 5 . 6 7 . 0 5 . 10 ma v v v r vccldrv choose a transistor with (min) of 50. the maximum input voltage is assumed 13.5 v, ma ma v 10 9 700 5 . 6 7 . 0 5 . 13 ? ? ? ? ? thermistor r hotset3 and over temperature setting resistors r hotset1 and r hotset2 choose ntc thermistor r hotset3 =2.2k ? , which has a constant of b hotset3 =3520, and the ntc thermistor resistance at the allowed maximum temperature t max is, ? ? ? ? ? ? ? ? 142 )] 25 273 1 115 273 1 ( * 3520 [ * 10 * 2 . 2 )] 1 1 ( * [ * 3 _ _ 3 3 exp t t b exp r r room max l hotset hotset tmax select r hotset2 = 931 ? to linearize the ntc, which has non-linear characteristics in the operational temperature range. then calculate r hotset1 corresponding to the allowed maximum temperature tmax. ? ? ? ? ? ? ? ? k vccl r r r hotset tmax hotset 63 . 3 6 . 1 ) 6 . 1 7 ( * ) 931 142 ( 6 . 1 ) 6 . 1 ( * ) ( 2 1 , choose r hotset1 =3.65k ? . IR3502B page 33 of 38 v3.2 ir3502 frequency vs. rosc resistor 5 10 15 20 25 30 35 40 45 50 55 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 frequency (khz) rrosc (kohm) rrosc nominal spec figure 18: frequency variation with rosc. i(vsetpt) vs. 1/rrosc 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 0.000 0.020 0.040 0.060 0.080 0.100 0.120 0.140 1/rrosc (1/kohm) i(vsetpt) (ua) i(vsetpt) min v(isetpt) nom v(isetpt) max v(isetpt) figure 19: isetpt with rosc. IR3502B page 34 of 38 v3.2 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of the pcb layout, therefore minimizing the noise coupled to the ic. ? dedicate at least one middle layer for a ground plane lgnd. ? connect the ground tab under the control ic to lgnd plane through a via. ? place vccl decoupling capacitor vccl as close as possible to vccl and lgnd pins. ? place the following critical components on the same layer as control ic and position them as close as possible to the respective pins, r osc , r vdac , c vdac , and c ss/del . avoid using any via for the connection. ? place the compensation components on the same layer as control ic and position them as close as possible to eaout, fb, vo and vdrp pins. avoid using any via for the connection. ? use kelvin connections for the remote voltage sense si gnals, vosns+ and vosns-, and avoid crossing over the fast transition nodes, i.e. switching n odes, gate drive signals and bootstrap nodes. ? avoid analog control bus signals, vdac, iin, and especi ally eaout, crossing over the fast transition nodes. ? separate digital bus, clkout, phsout and phsin from the analog control bus and other compensation components. hotset vccldrv pgood imon enable vosns ? to phase ics digital to vccl gnd ss/del vdac iin vrhot vsetpt vid3 vid4 rosc vid5 vid6 vid7 vccl r tcmp3 phsout clkout phsin vid2 vid1 vid0 c mon r mon c vccl2 to system c cp1 r hotset2 r hotset1 vdac_buff vn vdrp vosns + vo fb eaout r drp r ctmp1 r tcmp2 c vdac r vdac r osc css/de l r setpt to regulato r to rtherm r fb r fb1 c fb c cp r cp lgnd plane voltage remote sense to phase ics analog to thermisto r r mon1 IR3502B page 35 of 38 v3.2 pcb metal and component placement ? lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be 0.2mm to prevent shorting. ? lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensure s a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) ? four 0.30mm diameter vias shall be placed in t he center of the pad land and connected to ground to minimize the noise effect on the ic. ? no pcb traces should be routed nor vias placed under any of the 4 corners of t he ic package. doing so can cause the ic to rise up from the pcb resulting in poor solder joints to the ic leads. IR3502B page 36 of 38 v3.2 solder resist ? the solder resist should be pulled away from the me tal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always ensure nsmd pads. ? the minimum solder resist width is 0.13mm. ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ? the land pad should be solder mask defined (smd), wi th a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mi s-alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ? ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. ? the vias in the land pad should be tented or plugged from bottom boardside with solder resist. IR3502B page 37 of 38 v3.2 stencil design ? the stencil apertures for the lead lands should be app roximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, t he stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. ? the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. ? the land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease t he incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. IR3502B page 38 of 38 v3.2 package information 32l mlpq (5 x 5 mm body) ? ja = 24.4 o c/w, jc =0.86 o c/w data and specifications subject to change without notice. this product has been designed and qualified for the consumer market. qualification standards can be found on ir?s web site. ir world headquarters: 233 kansas st., el segundo, califor nia 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . www.irf.com |
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